Monolithic ICs generally comprise a number of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated over a planar substrate, such as a silicon wafer. While Moore's Law has held true for decades within the IC industry, scaling of IC dimensions is becoming more difficult with the most advanced MOSFET gate dimensions now below 20 nm. As device sizes continue to decrease, substrate films that are patterned during an etching process have reduced thicknesses and feature sizes, which are increasingly intolerant to the stripping processes employed to remove sacrificial etch mask materials. This is particularly true for the most critical patterning layers, such as gate electrode patterning and gate contact patterning because the fine geometries at these operations place the most extreme constraints on the masking material performance and etch processes. As a result, an etch mask may have a material composition (either as deposited, or as modified by an etch process employed to pattern the substrate layer) that is difficult to remove with sufficient selectivity relative to the substrate layer to avoid collateral damage to non-sacrificial etched features.
Techniques and structures for removing sacrificial etch masks without damaging the sensitive etched substrate layers would therefore be advantageous.